1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a phase locked loop (PLL) having a multi-level voltage-current converter and a method for locking a clock phase using multi-level voltage-current conversion.
2. Discussion of the Related Art
In general, when a clock is needed to operate an integrated circuit in a synchronous system and it receives an external clock signal, a phase locked loop (hereinafter, referred to as a PLL) circuit is used to phase-lock the external clock signal to the internal clock signal.
In a conventional semiconductor integrated circuit, a PLL circuit is used in a cache memory device for improving the speed of data processing between a central processing unit (CPU) and a dynamic random access memory (DRAM) of a computer or in a high-speed memory device such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM). A PLL circuit is also used to detect locking signals during recording processes in optical disks. Optical disks such as audio-CDs, CD-ROMs, or DVDs have a locking signal and data magnetically recorded simultaneously whenever a unit of data begins to be recorded. When reproducing recorded data, optical disk reproducing devices detect a sync signal and perform a locking operation, thereby reading recorded data. As a supply voltage of an integrated circuit decreases, a tuning voltage, which controls a voltage controlled oscillator (hereinafter, referred to as a “VCO”) of the PLL circuit included in the integrated circuit, also decreases. Since an output frequency of the VCO depends on the tuning voltage, when the tuning voltage level decreases, the output frequency of the VCO also decreases. Hence, it is difficult to design a PLL circuit with a wide frequency range while also having a low tuning voltage.
FIG. 1 illustrates a conventional PLL circuit. Referring to FIG. 1, a PLL circuit 100 includes a phase detector 110, a charge pump unit 120, and a VCO 130. The phase detector 110 detects a phase difference between a reference clock signal REF_CLK and an output clock signal FCLK output from the VCO 130 and generates an up signal UP or a down signal DOWN based on the detected phase difference. The charge pump unit 120 generates a predetermined tuning voltage Vc in response to the up signal UP or the down signal DOWN and controls the VCO 130. The VCO 130 receives the tuning voltage Vc and generates the output clock signal FCLK with a frequency proportional to the tuning voltage Vc. The PLL circuit 100 repeats the aforementioned feedback operation several times until the output clock signal FCLK is phase-locked to the reference clock signal REF_CLK.
The VCO 130 is a core component of the PLL circuit 100 and must be designed to have a wide range of frequency domains in proportion to the tuning voltage Vc. FIG. 2 is a graphical illustration of the relationship between the frequency of the output clock signal FCLK and the tuning voltage Vc. Referring to FIG. 2, ideally, the frequency of the output clock signal FCLK increases from 640 MHz to 1.1 GHz, as the tuning voltage Vc increases from 600 mV to 1.8V, i.e., the frequency of the output clock signal FCLK has a linear property.
Since, when the supply voltage of the integrated circuit decreases, the operating voltage of the PLL circuit 100 also decreases, this leads to the decrease of both the level of the tuning voltage Vc and the frequency of the output clock signal FCLK. Thus, when a system including the PLL circuit 100 operates at a high frequency, the system performance decreases because of the decrease in the frequency of the clock signal output from the PLL. One way to cure this phenomenon is to increase the change rate of the frequency of the output clock signal FCLK according to the changes in the tuning voltage Vc of the VCO 130 of the PLL circuit 100. However, this method increases phase noise of the PLL circuit 100.
To reduce phase noise, a plurality of VCOs can be used to generate output clock signals in different oscillating frequencies according to the level of the tuning voltage Vc. However, the use of the plurality of VCOs results in high power consumption, and increases the complexity of circuit configuration.
A need therefore exists for a PLL circuit that generates an output clock signal having a wide frequency band, and also has reduced phase noise and low power consumption.